1. Field of the Invention
The present invention-relates to a static random access memory, and more particularly to a static random access memory with a double vertical channel structure suitable for a highly integrated memory element and a method of the same.
2. Description of the Prior Art
Among various semiconductor memory elements, dynamic random access memories have only one transistor and one capacitor in every memory cell, whereas static random access memories (SRAM) have four transistors and two load resistors made of polysilicon material or six transistors in every memory cell. Due to such a complex structure, SRAMs are very restricted by the degree of integration. In order to solve this problem, research for developing highly integrated SRAMs is actively progressing.
FIG. 3 illustrates a circuit of a conventional SRAM cell. As shown in FIG. 3, the SRAM includes four transistors Q1 to Q4 and two load resistors R1 and R2 in every memory cell, all being connected with one another.
The operation of the SRAM having the structure of FIG. 3 will now be described. First, in a write operation, a source voltage V.sub.DD from a power source is applied to a word line W/L. At the same time, a bit line BL is also supplied with the source voltage V.sub.DD (that is, a Critical voltage V.sub.th), while a bit line BL is supplied with 0 V. The voltage from the bit line BL is applied to a node a, via the transistor Q1, while the voltage from the bit line BL is applied to a node b, via the transistor Q2. The voltages applied to nodes a and b are applied to transistors Q4 and Q3, as gate voltages, respectively. As the voltage V.sub.DD from the bit line BL supplied to the node a is applied to the transistor Q4 as the gate voltage, the transistor Q4 is turned on. On the other hand, since the voltage (0 V) from the bit line BL supplied to the node b is applied to the transistor Q3 as the gate voltage, the transistor Q3 is turned off. Thus, one data bit is stored.
On the other hand, in a stand-by state, an electric charge is charged in capacitive components which are formed parasitically at nodes a and b. At this time, the word line W/L is supplied with 0 V, so that gate voltages of transistors Q3 and Q4 become 0 V, thereby causing the transistors Q3 and Q4 to be turned off. However, a leakage current is presented in capacitive components of nodes a and b, so that electric charges of capacitor components are gradually discharged into the ground GND. As a result, if the leaked electric charge is not supplied, data stored In the SRAM disappears. In order to avoid this phenomenon, load resistors R1 and R2 are connected between the power source V.sub.DD and the node a and between the power source V.sub.DD and the node b, respectively. With such an arrangement, electric charge corresponding to the amount of leaked electric charge is supplied, so that a constant quantity of electric charge tan be maintained in the parasitic capacitive components.
In read operation, the word line W/L is supplied again with the source voltage V.sub.DD which is then distributed to nodes a and b and bit lines BL and BL. At this time, the voltage at bit line BL is relatively high, while the voltage at bit line BL is relatively low, because the electric charge from the bit line BL is discharged via transistors Q2 and Q4 into the ground GND. Accordingly, the data read operation of the SRAM is to sense the voltage difference between bit lines BL and BL. At this time, the voltage of bit line BL is determined by resistance values of transistors Q2 and Q4 at their ON-states. The lower the resistance value of transistor Q4 at its ON-state, the lower the voltage of node b. At the higher resistance value of transistor Q2 at its ON-state, the influence of the voltage of bit line BL on the voltage of node b is reduced. As a result, it is possible to prevent efficiently an inversion of data in the read operation.
FIG. 4 is a sectional view of a typical conventional SRAM. A method of making this SRAM will now be described, in conjunction with FIG. 4.
First, a silicon substrate 50 having a high resistance is subjected to an ion injection and then a diffusion, thereby forming p-type wells 51 and 52 thereon. Subsequently, a LOCOS (local oxidation of silicon) process is performed, to form field regions 53 for isolating transistors from one another. On the entire surfaces of p-type wells 51 and 52 and field regions 53 is grown a gate oxide film 54. On the gate oxide film 54 is deposited a polysilicon layer which is then subjected to a photo lithography method and an etching method, to form gate electrodes 55.
Although not shown in FIG. 4, a side wall may be then formed on the side surface of each gate electrode 55, so as to produce a transistor having a lightly doped drain structure. Source/drain regions 56 are formed at opposite sides of each gate electrode 55, by injecting n-type ions into p-type wells 51 and 52 disposed at the sides and then diffusing them.
On the entire exposed surfaces, an oxide film 57 is deposited using a CVD (chemical vapor deposition (CVD) method. The oxide film 57 is then subjected to the photo lithography method and the etching method, thereby forming interconnection lines for connecting transistors with one another and buried contacts to which source/drains 56 are connected.
Thereafter, a polysilicon layer is deposited on the entire exposed surface by using the CVD method. The polysilicon layer is subjected to the photo lithography method and the etching method, thereby forming interconnection lines 58. Ions of a conductivity opposite to that of the interconnection lines 58 are injected into the remaining polysilicon layer thereby forming load resistors 59.
By using the CVD method, a boron phosphorous silicate glass (BPSG) layer is deposited on the entire exposed surface. The BPSG layer 60 is subjected to the photo lithography method and the etching method so that buried contacts are formed above source/drain regions.
Subsequently, an aluminum layer is deposited on the entire exposed surface, using the CVD method, and then subjected to the photo lithography method and the etching method, to remove unnecessary portions thereof, thereby forming source/drain electrodes 61. On the entire exposed surface, a Si.sub.3 N.sub.4 film 62 is then formed as a passivation layer. Thereafter, bit lines and word lines are formed on the passivation layer. Since the formation of bit lines and word lines has no relation with the feature of the present invention, a detailed description therefor is omitted.
However, the above-mentioned conventional structure is restricted by a reduction in the memory cell size. That is, the conventional SRAM includes horizontally formed channel regions of transistors which limit a reduction in the memory cell size, since adjacent channel regions have to maintain a pitch of not less than the minimum line width therebetween. As a result, it is impossible to obtain a desired chip size and still meet the high integration of SRAM.